The present invention relates to an active matrix type liquid crystal display panel and a method of driving the display panel.
In recent years, attention has been paid to a liquid crystal display panel which is driven by a thin film transistor (hereinafter simply referred to as "TFT"). A TFT matrix array for dividing the liquid crystal display panel generally has the following structure. That is, m gate lines and n data lines are arranged on a display screen so that the gate lines are perpendicular to the data lines, to divide the display screen into m.times.n display pixels. Each gate line is driven by a gate line drive circuit, and each data line is driven by a data line drive circuit. A TFT is provided at a position where a gate line and a data line face each other, and the switching function of the TFT is utilized to control the application of picture information to each pixel. Thus, a picture image is displayed on that region of a liquid crystal layer provided on the TFT matrix array which corresponds to the pixels, in accordance with the picture information.
In the above display panel, however, there arises a problem that, in a period when a TFT is kept at an OFF-state and picture information is held by a pixel corresponding to the TFT, a video signal indicating the picture information is degraded by the self-discharge in the liquid crystal layer and the leakage current at the TFT. In order to solve this problem, an additional storage capacitor is usually provided for each pixel. A method of forming the additional storage capacitor is described in an article (IEEE Transaction of Electron Devices, Vol. ED-20, No. 11, 1973, pages 995 to 1,001). In this method, the additional storage capacitor is formed between a pixel electrode and a gate line adjacent thereto.
Further, in a liquid crystal display panel driven by a TFT, there arises another problem that, owing to the parasitic capacitance C.sub.gs between the gate and source electrodes of the TFT, a gate voltage pulse capacitively couples to the pixel electrode voltage. Such a capacitive coupling the gate voltage pulse occurs as follows. Referring to FIG. 22, the parasitic gate-source capacitance (C.sub.gs) 106 is annexed to a TFT 104. When a gate line voltage V.sub.g and a data line voltage V.sub.d each shown in FIG. 23 are applied to a gate line x.sub.i and a data line y.sub.i which are connected to the TFT104, respectively, a pulse voltage applied to the gate line x.sub.i, leaks to the pixel electrode by an amount .DELTA.V through the parasitic capacitance C.sub.gs. Such a gate pulse voltage occurs in synchronism of the ON-OFF operation of the TFT. Specifically, a change in potential of the pixel electrode caused by the capacitive coupling the gate pulse voltage at a time the TFT is turned off, is kept for a long time. Thus, as shown in FIG. 24, the center potential V.sub.sc of the potential waveform V.sub.s of the pixel electrode deviates from the center potential V.sub.dc of the data line by an amount .DELTA.V. While, a potential V.sub.com shown in FIG. 24 is applied to an opposite electrode (namely, a transparent electrode opposite to the pixel electrode). Thus, a d.c. voltage equal to .vertline.V.sub.com -V.sub.sc .vertline. is applied across the pixel. The generation of this d.c. voltage brings about the degradation of display characteristics, the degradation of alignment characteristics of liquid crystal and a reduction in life of the pixel electrode, thereby generating a non-uniform image, latent image and a flicker.
In order to solve this problem, the following method has been devised. That is, when a gate pulse is applied to a TFT connected to a gate line, a pulse opposite in polarity to the gate pulse is applied from the preceding gate line to a pixel electrode connected to the TFT, through an additional storage capacitor formed between the pixel electrode and the preceding gate line. This method is described in, for example, a Japanese Patent Application JP-A-59-119,390.